Date: Thu, 28 Jul 2005 04:20:56 -0500 (CDT) From: Alan L. Stone Subject: Updates: Testing, ATCs, Mock-up, Etc. Dear All, Hopefully, you can follow my train of thought in this email. There are a lot of overlapping concerns. Jorge and I spent a couple of hours on Wed afternoon going over the MSU testing proposal, which he has documented here: http://hep.pa.msu.edu/people/benitez/adf/attm/ I think is well-detailed, clear and the "paper trail" is just what we need. In short, a Patch Panel Card (PPC), two Pleated Foil Cables (PFC) and one ADF Transition Card (ATC) will be tested in conjunction. However, there are some additional considerations. a) After Jorge went through the full set of ATCs - we have 27 at Fermilab, and there is one at MSU - only 10 ATCs at Fermilab are "unwarped". In other words, 17 of the ATCs are flagged as bad because there is a clear bow along the vertical axis.** Flexing the warped ATCs while plugging them into the ADF backplane as is an unacceptable risk in my opinion. We only have 10 ATCs for ADF-to-TAB testing for the short term. ** An attempt had been made to straighten these boards after they arrived from the vendor by baking them and cooling under tension. This appeared to work, but within a day or two, the board "memory" restored the warping. On the remaining production order (same vendor: Pentaplex), a straightening specification was made. The expected delivery date of 87 boards is Aug 10th. Add a few more days for stuffing. That will give us 97 ATCs in total (before testing). We need 80 for the final system. b) It would make sense to number the boards and label the cables after the set has passed the MSU tests. Each PPC and ATC has a white box on which one can write in a serial number. The cable labels for the PFCs were already printed by Peter Renkel and Cosmin Dragoiu last month. c) The patch panel assemblies, cable routing and strain relief mechanisms need to be exercised with real components. Up to this point, the only mechanical mock-up done was for the labelling and redressing of BLS trigger cables. Over the past couple of months, John Fogelsong and Victor Martinez have done an impressive job. The cable routing schematics can be found here: http://www-ppd.fnal.gov/EEDOffice-w/Projects/dzero/L1_Cal_Trig_Patch_Panel/noncable_lvl2a.html We need to use 20 PPCs (we have 25 in hand, and 75 more ordered) and 40 PFCs for this excercise. Jorge and I involved John Fogelsong to determine the best strategy. We also had a little debate on how to place the PFC cable label. We decided on the following: 1) Jorge will proceed with the MSU tests on the 10 available sets (limited by 10 good ATCs). He had already done 1. He needs about an hour per set, and use of the ADF crate. 2) We have 192 PFCs. The first batch of 31 PFCs were tested by Rahmi Unalan and Cosmin back in late May following instructions from Dan Edmunds. Jorge will pull PFCs for his tests from the untested batch of 161 PFCs. 3) Two more patch panel assemblies will be installed at the sidewalk test stand on Thursday. The goal is to simulate the routing for all PFCs which plug into a single ADF backplane, in this case ADF Crate B in M106: http://www-ppd.fnal.gov/EEDOffice-w/Projects/dzero/L1_Cal_Trig_Patch_Panel/pdf/PFC_RoutingM105_107_434269.pdf 4) After each set has passed the MSU testing, Jorge will fill out the checklist and trailer sheet, and then assign a serial number to the ATC and PPC. The labels for the PFCs will follow from the above schematic (PFC041-PFC060).** One has to label both ends of each cable. ** The white tab (with printed text) of the label goes on first, about one inch from the connector head, and on the same flat side of the cable as the long edge of the connector. This way, the text will face out and always be visible when you lower the patch panel. 5) After the 10 sets are done, we will have 10 ATCs, 10 PPCs and 20 PFCs. For the mock-up, ideally, I would like double that, but I definitely need 40 PFCs with labels. The labels define everything: rack, crate, card, left/right, up/down. Therefore, we will pull 20 PFCs from the batch already tested by Rahmi and Cosmin, and apply the labels. I can use 10 untested PPCs. 6) I'll do the mock-up on Friday, or if Jorge needs more time, then over the weekend. If any one would like to assist me on this exercise let me know. The routing of the ADF-to-TAB LVDS cables has also been given significant thought and design. http://www-ppd.fnal.gov/EEDOffice-w/Projects/dzero/L1_Cal_Trig_Patch_Panel/pdf/LVDS_RoutingM103_112_434267.pdf (Note: Almost correct - there are a couple of things that were already fixed, but the latest version hasn't propagated to the web page yet). In fact, it requires more effort than the PFC routing because: a) All cables are 5 meters long to avoid time skewing but the distance between each ADF and TAB crate is different. Where and how do you store the slack? b) At the moment, there are four horizontal bars on the TAB/GAB backplane. John and I propose removing them - they would get in the way. A new strain relief mechanism needs to be devised for the TAB/GAB crate; one is already in place for both PFCs and LVDS cables at the ADF backplane. c) With 10 ATCs, we can string 30 LVDS cables to the TAB/GAB backplane. How should they be distributed to the TAB inputs? The glenair test board should be ready early next week. The first candidate for component testing is a PPC which did not pass the MSU test. Jorge reported there is a problem with one channel. With the glenair test board, we can also test the PPC monitor connectors and the ATC LVDS outputs, and we do not compete for use of the ADF crate. Alan ------------------------------------------- | Alan L. Stone | Office: PK177 #57 | | Fermilab | Work: (630) 840-8581 | | PO Box 500 | Fax: (630) 840-8886 | | D0/MS 352 UIC | alstone@fnal.gov | | Batavia, IL 60510 | | | http://www-clued0.fnal.gov/~alstone | -------------------------------------------